The fabrication of large scale integrated semiconductor devices requires fabrication methods having small tolerance ranges. Thus, when fabricating trench transistors, by way of example, care must be taken to ensure that contact holes which are formed in mesa regions situated between the trenches (that part of the semiconductor body—in which the trenches are formed—which is situated between the trenches) are at a defined distance from the trenches. If this is not the case, then the threshold voltage of the trench transistor is subject to large fluctuations.
The fabrication of contact holes in mesa regions is generally effected using so-called “spacers”. The spacers are fabricated before the formation of the contact holes and define the later spacing between the trenches and the contact holes to be fabricated. Several methods are taken into consideration:
In the document DE 40 42 163 C2 the spacers are fabricated using complicated masks.
In the document DE 102 45 249 A1 the spacers are fabricated using insulation structures which have to be produced separately.
In the document U.S. Pat. No. 5,385,852, the spacers required for producing the contact holes are produced using a trench mask.
In the document US 2002/0008284 A1, the spacers are produced by means of a mesa region etching-back process.
Furthermore, reference shall be made to the document U.S. Pat. No. 5,801,417, in which the spacers are fabricated using a hard mask.
The methods described above have the disadvantage that the tolerances which occurred during the fabrication of the spacers are relatively large. Moreover, masks are additionally required for fabricating the spacers.